How should cache maintenance operations be handled in systems with multi-level cache, with reference to DMA?

Applies to: Cortex-A9, Processor Cores

Answer

In systems with multiple layers of caches, some care is needed when performing cache maintenance activity where the implementation does not provide atomic cache maintenance operations. This means systems where cache maintenance must be performed separately on L1 and L2 caches. Examples of such systems include Cortex-A9 coupled with L2C-310, or Cortex-A5 coupled with L2C-310. A particular area of concern is where there are multiple CPUs sharing L2 cache and there is a possibility that one CPU may access memory while another CPU is performing cache maintenance operations. ARM processors provide three kinds of cache maintenance operation, with provision for such operations to be broadcast between processors in an MPCore system. Such operations may be required when an external DMA is available in the system and is not participating in automatic cache coherency management.

• Clean and invalidate. This is intended to be used for cache-shutdown type operations. It is not generally approriate for handling DMA.
• Clean. This should be done when data changed by the ARM CPU needs to be made visible to external observers (such as a DMA). If atomic cache maintenance operations are not provided by the system, cleaning must proceed outwards, (innermost cache first, outermost cache last).
• Flush/Invalidate. This should be done when data changed by an external DMA agent needs to be made visible to the CPU. When atomic cache maintenance operations are not available, invalidation must be done inwards, with the outermost cache being invalidated first and the innermost last.