The difference between FIQ and IRQ interrupt system in any microprocessor...Eg:ARM926EJ
Ans1. A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter is unstacked.
In other words, an FIQ is just a higher priority interrupt request, that is prioritized by disabling IRQ and other FIQ handlers during request servicing. Therefore, no other interrupts can occur during the processing of the active FIQ interrupt.
Ans 2. An FIQ interrupt is higher priority than an IRQ, it has its own mode (and therefore r13, r14 and spsr) and mask bit (CPSR[6]), which allows it to be taken while an IRQ is being handled - the processor can store enough state to enable the programmer to return to the IRQ handler after handling the FIQ. Further, the extra banked registers and the address of the FIQ vector
allows the programmer to build systems for which the interrupt latency for an FIQ is less than for an IRQ.
In a typical system there will be one FIQ (the highest priority or most critical interrupt) sources and a number of IRQ sources, arbitrated by an interrupt handler.
Please check out my another post in the same blog.
Ans1. A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter is unstacked.
In other words, an FIQ is just a higher priority interrupt request, that is prioritized by disabling IRQ and other FIQ handlers during request servicing. Therefore, no other interrupts can occur during the processing of the active FIQ interrupt.
Ans 2. An FIQ interrupt is higher priority than an IRQ, it has its own mode (and therefore r13, r14 and spsr) and mask bit (CPSR[6]), which allows it to be taken while an IRQ is being handled - the processor can store enough state to enable the programmer to return to the IRQ handler after handling the FIQ. Further, the extra banked registers and the address of the FIQ vector
allows the programmer to build systems for which the interrupt latency for an FIQ is less than for an IRQ.
In a typical system there will be one FIQ (the highest priority or most critical interrupt) sources and a number of IRQ sources, arbitrated by an interrupt handler.
Please check out my another post in the same blog.
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