Embedded Hardware : I2C

Features of the I2C-bus(From the Specification)
1.Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).

2.Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers.

3.It is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer.

4.Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode.

5.On-chip filtering rejects spikes on the bus data line to preserve data integrity.

6.The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance. More capacitance may be allowed under some conditions.

"I2C communication uses a 7bit address space with 16 reserved addresses, so a theoretical maximum of 112 nodes can communicate on the same bus.In practice, however, the number of nodes is limited by the specified total bus capacitance of 400pF, which restricts communication distances to a few meters"


The bus has two roles for nodes,master and slave:-
A master issues the clock, and the slave addresses and also initiates and ends data transactions.A slave receives the clock,and addresses and responds to requests from the master.

The master initiates a transaction by creating a start condition,followed by the 7bit address of the slave with which it wishes to communicate.This is followed by a single read/write bit, representing whether the master wishes to write to (0), or to read from (1) the slave.The master then releases the SDA line to allow the slave to acknowledge the receipt of data.

The slave responds with an acknowledge bit (ACK) by pulling SDA low during the entire high time of the ninth clock pulse on SCL, after which the master continues in either transmit or receive mode (according to the R/W bit sent), while the slave continues in the complementary mode (receive or transmit, respectively).The address and the 8bit data bytes are sent most significant bit first.The start bit is indicated by a high-to-low transition of SDA while SCL is high.The stop condition is created by a low-to-high transition of SDA while SCL
is high.

If the master writes to a slave,it repeatedly sends a byte with the slave sending an ACK bit. In this case,the master is in master-transmit mode and slave is in slave-receive mode.

If the master reads from a slave, it repeatedly receives a byte from the slave,while acknowledging (ACK) the receipt of every byte but the last one.In this situation,the master is in master-receive mode and slave is in slave-transmit mode.

The master ends the transmission with a stop bit or may send another start bit to maintain bus control for further transfers.When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when receiving acknowledgment from the slave.When reading from a slave,the master starts in transmit-mode and then changes to receive-mode after sending a read request (R/W bit = 1) to the slave.The slave continues in the complementary mode until the end of a transaction.Note that the master ends a reading sequence by not acknowledging (NACK) the last byte received.This procedure resets the slave state machine and allows the master to send the stop command.

Clock Synchronization

Under normal conditions, only one master device generates the clock signal, SCL. During the arbitration procedure,however,there are two or more masters and the clock must be synchronized so that the data output can be compared. The wired-AND property of SCL means that a device that first generates a low period on SCL (device #1) overrules the other devices.At this high-to-low transition, the clock generators of the other devices are forced to start their own low period. The SCL is held low by the device with the longest low period.The other devices that finish their low periods must wait for SCL to be released,before starting their high periods.A synchronized signal on SCL is obtained, where the slowest device determines the length of the low period and the fastest device determines the length of the high period.If a device pulls down the clock line for a longer time, the result is that all clock generators must enter the wait state. In this way, a slave slows down a fast master and the slow device creates enough time to store a received data word or to prepare a data word to be transmitted.

Arbitration

Several I2C multi-masters can be connected to the same I2C bus and operate concurrently.By constantly monitoring SDA and SCL for start and stop conditions,they can determine whether the bus is currently idle or not. If the bus is busy, masters delay pending I2C transfers until a stop condition indicates that the bus is free again.

However, it may happen that two masters start a transfer at the same time. During the transfer, the masters constantly monitor SDA and SCL. If one of them detects that SDA is low when it should actually be high, it assumes that another master is active and immediately stops its transfer. This process is called arbitration.

What are the limitations of I2C interface?

• Half-duplex communication, so data is transmitted only in one direction (because of the single data bus) at a time.
• Since the bus is shared by many devices, debugging an I2C bus (detecting which device is misbehaving) for issues is pretty difficult.
• The I2C bus is shared by multiple slave devices if anyone of these slaves misbehaves (pull either SCL or SDA low for an indefinite time) the bus will be stalled. No further communication will take place.
• I2C uses resistive pull-up for its bus. Limiting the bus speed.
• Bus speed is directly dependent on the bus capacitance, meaning longer I2C bus traces will limit the bus speed.